Accurate estimation of global buffer delay within a floorplan
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
RC delay metrics for performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
D. Karger
A.B. Kahng
J.H. Huang
C.N. Sze
S.S. Sapatnekar
Jiang Hu
Delay and slew metrics using the lognormal distribution
Interconnect Optimization Considering Multiple Critical Paths