Multi-core Aware Process Mapping and its Impact on Communication Overhead of Parallel Applications
Design of interleaved multithreading for Network Processors on Chip
Evaluating Thread Placement Based on Memory Access Patterns for Shared Cache Multi-core Processors
TLP and ILP exploitation through a Reconfigurable Multiprocessor System
Parallel Shared-Memory Workloads Performance on Asymmetric Multi-core Architectures
Philippe Olivier Alexandre Navaux
Marco Antonio Zanata Alves
Eduardo Rocha Rodrigues
Henrique Cota de Freitas
Jairo Panetta
MATTHIAS Diener