Paper

DEEP: An Iterative FPGA-based Many-Core Emulation System for Chip Verification and Architecture Research, December 2010

J. Ributzka, Y. Hayashi, F. Chen, and G. Gao. CAPSL Technical Memo 103: DEEP: An Iterative FPGA-based Many-Core Emulation System for Chip Verification and Architecture Research, December 2010.

2010

Created by ACM worker at 2019-04-15 14:25:27.0.
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