Model order-reduction of RC(L) interconnect including variational analysis
TACO
Calculating worst-case gate delays due to dominant capacitance coupling
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 34th annual conference on Design automation conference - DAC ’97
Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC ’99
Proceedings of the 37th conference on Design automation - DAC ’00
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD ’98
Karthik Rajagopal
Ravishankar Arunachalam
Florentin Dartu
Andrzej J. Strojwas
Ying Liu
Paul D. Gross
Timed pattern generation for noise-on-delay calculation
A quasi-convex optimization approach to parameterized model order reduction