ACM - affordances
Shekhar Borkar
Future system-on-silicon LSI chips
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
Teraflop Prototype Processor with 80 Cores
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs