A Simulator for SMT Architectures : Evaluating Instruction Cache Topologies

GONÇALVES, R. A. L. ; AYGUADE, E. ; VALERO, M. ; NAVAUX, P. O. A. . A Simulator for SMT Architectures : Evaluating Instruction Cache Topologies. In: 12º Synoisium on Computer Aechitecture and High-Performance Computing, 2000, São Pedro. Anais. Porto Alegre: SBC, 2000.

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