Paper

Interconnect Optimization Considering Multiple Critical Paths

2018

Created by Alysson Bolognesi Prado at 2019-03-28 10:05:00.0.

Simplified Graph of Associations

Word Cloud

Bibliographic Sets

1

Research Paradigm

Authors

7

Venue

1

Proceedings of the 2018 International Symposium on Physical Design - ISPD ’18

References

17

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages

New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Interconnect layout optimization by simultaneous Steiner tree construction and buffer insertion

Placement driven synthesis case studies on two sets of two chips: hierarchical and flat

San Jose, California