Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets
The Elmore delay as a bound for RC trees with generalized input signals
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design, Automation and Test in Europe
Xin Li
N. Menezes
S. Pullela
S.R. Nassif
F. Liu
Peng Li
A quasi-convex optimization approach to parameterized model order reduction
Delay and slew metrics using the lognormal distribution