A Simulator for SMT Architectures : Evaluating Instruction Cache Topologies
Performance evaluation of decoding and dispatching stages in Simultaneous Multithreaded Architectures
A Vector-µSIMD-VLIW Architecture for Multimedia Applications
2005 International Conference on Parallel Processing (ICPP’05)
Ronaldo Augusto de Lara Goncalves
E. AYGUADE
Philippe Olivier Alexandre Navaux
E. Salami
DRMA: Dynamically Reconfigurable MPSoC Architecture