Paper

Technology Flavor Selection and Adaptive Techniques for Timing-constrained 45Nm Subthreshold Circuits

2009

Created by Alysson Bolognesi Prado at 2017-03-16 11:20:41.0.

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Bibliographic Sets

2

ACM - affordances

Research Paradigm

Authors

3

Jean-Didier Legat

References

13

Nanometer device scaling in subthreshold logic and SRAM

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

Exploring variability and performance in a sub-200-mV processor

Analysis and mitigation of variability in subthreshold design

Statistical Timing Analysis: From Basic Principles to State of the Art

Design and optimization of dual-threshold circuits for low-voltage low-power applications