Improving Performance trough Speculative Trace Reuse
Preceding Trace Inpts with Dynamic Trace Memoization: Determining Speedup Upper Bounds
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Value Predictors for Reuse trough Speculation on Traces
A Speculative Trace Reuse Architecture with Reduced Hardware Requirements
Uma Abordagem Branch and Bound Para o RCPSP em um Ambiente de Computação Colaborativa Congreso Latino Iberoamericano de Investigación de Operaciones, CLAIO, Havana, Cuba, Outubro de 2004
Amarildo Teodoro da Costa
Philippe Olivier Alexandre Navaux
Maurício Lima Pilla
B. CHILDERS
Felipe Cesar PEREIRA
Fábio LOURENÇO