Improving Performance trough Speculative Trace Reuse
Preceding Trace Inpts with Dynamic Trace Memoization: Determining Speedup Upper Bounds
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Value Predictors for Reuse trough Speculation on Traces
A Speculative Trace Reuse Architecture with Reduced Hardware Requirements
Felipe Maia Galvão França
Philippe Olivier Alexandre Navaux
Maurício Lima Pilla
B. CHILDERS
M. L. SOFFA